1. Field of the Invention
The present invention relates to a semiconductor device and a semiconductor device fabrication method.
2. Description of the Related Art
At present, expectations are high with regard to the SOI (Silicon On Insulator) technique that involves forming a silicon layer on an insulation layer and forming electronic elements such as transistors on the silicon film. This is one technique for implementing low electrical power consumption and high speed operability of a semiconductor device. The introduction of the SOI technique to semiconductor products is being actively pursued. This insulation film is formed on a support substrate and is known as a BOX (Buried OXide) layer. The silicon film formed on the BOX layer is called the SOI layer. When a semiconductor substrate (SOI substrate) is made using the SOI technique, a marked reduction in the power consumption is realized compared with an ordinary silicon substrate (bulk-type substrate). In addition, the SOI substrate possesses a favorable high frequency characteristic so that the SOI substrate is widely adopted in semiconductor devices that have an analog circuit operating on high frequency bandwidth signals or an analog-digital hybrid circuit, for example.
Although a certain improvement with respect to the parasitic capacitance of the substrate may be seen in the high frequency circuit as a result of applying the SOI technique, there is a greater need for a reduction in the element dielectric loss caused by the substrate because, in current technology the frequency bandwidth of transmission signals often reaches the Gigahertz (GHz) range.
Japanese Patent Kokai (Laid Open Publication) No. 9-270515 discloses a technique for reducing the parasitic capacitance between the substrate and an element (inductor) of a semiconductor device that includes an SOI layer.
According to the semiconductor device described in Japanese Patent Kokai No. 9-270515, the SOI layer and an element isolation oxide film are formed on a BOX layer, and the inductor is disposed on the element isolation oxide film. On account of the small parasitic capacitance, not only does the element isolation oxide film prevent the generation of element dielectric loss, the film also fulfils the role of alleviating the dielectric loss of the inductor which is caused by the substrate.
The conventional technique needs to form an element, for which a dielectric loss reduction is sought, on a predetermined film such as an element isolation oxide film. This technique imposes restrictions on the layout, quantity and type of the elements for which the dielectric loss reduction is sought. Further, if the element isolation oxide film is formed thickly, the effect of the element dielectric loss reduction is large, but a corresponding difference in level (height) is produced between the region in which the element isolation oxide film is formed and another region. This difference in level will adversely affect the subsequent fabrication process.